Hardware Verification Engineer

About the role

Join our Hardware Verification team to build and maintain state-of-the-art UVM testbenches for complex digital SoCs. You will work alongside RTL designers to achieve full functional coverage on FPGA prototypes and final tapeout.

Responsibilities

• Develop constrained-random UVM testbenches in SystemVerilog for subsystem and full-chip verification.
• Write Python-based regression infrastructure and coverage analysis scripts.
• Collaborate with FPGA engineers on prototype bring-up and correlation to simulation.
• Track coverage closure and triage failing simulations.
• Contribute to formal verification flows (JasperGold, VC Formal).

Requirements

• 3+ years hardware verification with UVM methodology.
• Expert-level SystemVerilog for testbench development.
• Python scripting for regression automation.
• Experience with simulation tools: Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Bonus: formal verification (JasperGold), emulation (Palladium, ZeBu).